型号SN74LV4040A
品牌
分类计数器
描述12 位异步二进制计数器
相关操作
产品概述

参数

Function Counter
Bits (#) 12
Technology family LV-A
Supply voltage (min) (V) 2
Supply voltage (max) (V) 5.5
Input type Standard CMOS
Output type Push-Pull
Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)
Operating temperature range (°C) -40 to 85
Rating Catalog

封装 | 引脚 | 尺寸

PDIP (N) 16 181.42 mm² 19.3 x 9.4
SOIC (D) 16 59.4 mm² 9.9 x 6
SOP (NS) 16 79.56 mm² 10.2 x 7.8
SSOP (DB) 16 48.36 mm² 6.2 x 7.8
TSSOP (PW) 16 32 mm² 5 x 6.4
TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4
VQFN (RGY) 16 14 mm² 4 x 3.5

特性

  • 2-V to 5.5-V VCC Operation
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2.3 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Voltage Operation on All Ports
  • High On-Off Output-Voltage Ratio
  • Low Crosstalk Between Switches
  • Individual Switch Controls
  • Extremely Low Input Current
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

说明

The ’LV4040A devices are 12-bit asynchronous binary counters with the outputs of all stages available externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low. The count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay circuits, counter controls, and frequency-dividing circuits.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.