型号LF156QML
品牌
分类通用运算放大器
描述获得 QML 认证的军用级、单路、40V、5MHz、FET 输入运算放大器
相关操作
产品概述

参数

Number of channels 1
Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 44
Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 10
Rail-to-rail No
GBW (typ) (MHz) 5
Slew rate (typ) (V/µs) 12
Vos (offset voltage at 25°C) (max) (mV) 5
Iq per channel (typ) (mA) 5
Vn at 1 kHz (typ) (nV√Hz) 12
Rating Military
Operating temperature range (°C) -55 to 125
Offset drift (typ) (V/°C) 0.000005
Input bias current (max) (pA) 100
CMRR (typ) (dB) 100
Iout (typ) (A) 0.025
Architecture FET
Input common mode headroom (to negative supply) (typ) (V) 3
Input common mode headroom (to positive supply) (typ) (V) 0.1
Output swing headroom (to negative supply) (typ) (V) 2
Output swing headroom (to positive supply) (typ) (V) -2

封装 | 引脚 | 尺寸

TO-CAN (LMC) 8 80.2816 mm² 8.96 x 8.96

特性

  • Advantages
    • Replace Expensive Hybrid and Module FET Op Amps
    • Rugged JFETs Allow Blow-Out Free Handling Compared with MOSFET Input Devices
    • Excellent for Low Noise Applications Using Either High or Low Source Impedance—Very Low 1/f Corner
    • Offset Adjust Does Not Degrade Drift or Common-Mode Rejection as in Most Monolithic Amplifiers
    • New Output Stage Allows Use of Large Capacitive Loads (5,000 pF) Without Stability Problems
    • Internal Compensation and Large Differential Input Voltage Capability

Common Features

  • Low Input Bias Current: 30pA
  • Low Input Offset Current: 3pA
  • High Input Impedance: 1012Ω
  • Low Input Noise Current: 0.01 pA / √Hz
  • High Common-Mode Rejection Ratio: 100 dB
  • Large DC Voltage Gain: 106 dB

Uncommon Features

  • Extremely Fast Settling
    • Time to 0.01% 1.5μs
  • Fast Slew Rate 12V/µs
  • Wide Gain Bandwidth 5MHz
  • Low Input Noise Voltage 12 nV / √Hz

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说明

This is the first monolithic JFET input operational amplifier to incorporate well matched, high voltage JFETs on the same chip with standard bipolar transistors (BI-FET™ Technology). This amplifier features low input bias and offset currents/low offset voltage and offset voltage drift, coupled with offset adjust which does not degrade drift or common-mode rejection. The device is also designed for high slew rate, wide bandwidth, extremely fast settling time, low voltage and current noise and a low 1/f noise corner.